例句與造句

1. Design and implementation of a 64bit cmos parallel adder with modified architecture
   并行加法器設(shè)計(jì)與實(shí)現(xiàn)
2. Computers , 2005 , 54 : 225 - 231 . 2 brent r p , kung h t . a regular layout for parallel adders
   并行前綴加法器可分為g p產(chǎn)生部分進(jìn)位傳播部分或稱為進(jìn)位鏈以及結(jié)果產(chǎn)生部分。
3. It's difficult to find parallel adder in a sentence. 用parallel adder造句挺難的